imec, the Flemish semiconductor research hub, announced a breakthrough in memory technology that could ease the "memory wall" hindering modern AI systems. The institute unveiled the first three‑dimensional implementation of a charge‑coupled device (CCD) memory architecture, a concept originally used in digital cameras and scientific imaging. This new design repurposes CCD principles for data storage, stacking memory cells vertically much like 3D NAND while preserving the fast, rewritable nature of DRAM.
Unlike conventional DRAM, which arranges cells on a flat plane and suffers from leakage and escalating manufacturing costs, the 3D CCD hybrid leverages indium gallium zinc oxide (IGZO) as its semiconductor material. IGZO offers lower leakage currents, longer data‑retention times and compatibility with low‑temperature processing—traits that enable denser stacking of layers. In early tests, imec’s prototype achieved charge‑transfer rates exceeding 4 MHz, a promising start for a technology still in its infancy.
Program Director for Storage Memory Maarten Rosmeulen explained that the device operates at the block level rather than the byte level typical of DRAM. "Unlike byte‑addressable DRAM, our 3D CCD device is designed to provide block‑level data access, which is better suited to modern AI workloads," he said. This approach aligns with the pattern‑oriented data movement in large‑scale neural‑network training, where GPUs and accelerators spend more time waiting for data than performing calculations.
The hybrid architecture could also reduce wear mechanisms that limit NAND endurance. By combining DRAM‑like speed with NAND‑like density, the chip promises “unlimited endurance” for intensive AI applications, according to imec researchers. The team envisions integrating the memory as a buffer within a 3D NAND flash string, a cost‑effective path to scale bit density far beyond current DRAM limits.
Future development aims to position the chip as a CXL Type‑3 device, adhering to the Compute Express Link standard that connects CPUs, GPUs and accelerators. Hyperscalers are already turning to CXL as AI models outgrow the capacity of local GPUs, making a high‑bandwidth, low‑latency memory solution especially valuable.
Despite the promising results, imec acknowledges several hurdles remain. Scaling the layer count, managing thermal behavior and proving real‑world integration are cited as key challenges before commercial deployment. Nonetheless, the prototype demonstrates that a CCD‑based memory can move charge efficiently in three dimensions, opening a potential new class of memory architecture rather than a modest evolution of existing designs.
If the technology matures, it could slash the cost of AI infrastructure by reducing reliance on expensive DRAM. imec’s next phase will focus on expanding the stack to match commercial NAND chips, which now exceed 200 layers, and refining the manufacturing process to meet industry standards.
Este artículo fue escrito con la asistencia de IA.
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